1. Field of the Invention
The present invention relates to a semiconductor device with a trench isolation structure, and more particularly to a MOSFET having a trench isolation structure therein.
2. Description of the Related Art
A significant requirement in sub-micron high-performance semiconductor technologies is junction depth reduction in, for example, MOS (metal-oxide-semiconductor) source and drains and bipolar emitters and bases. Reducing the junction depth suppresses MOS (metal-oxide-semiconductor) transistor punch-through leakage and minimizes short channel effects such as drain-induced barrier lowering (DIBL) in CMOS devices. Devices junctions with relatively high dopant concentrations, ultra-shallow depths, low contact sheet resistances, and low junction leakage currents will be critical for advanced deep submicron technologies.
ULSI integrated Circuits having submicron channel lengths require scaling down of the geometries of devices, including the channel length of metal oxide semiconductor field effect transistors (MOSFETS or MISFET""s), which is the ubiquitous workhorse in ULSI circuits. The driving force behind scaling down channel length has been an increase of packing density of devices on a typical chip which has concomitant advantages of increased functionality as well as higher throughput for the process. However, the reduction of channel lengths has resulted in severe technological problems in terms of device performance and reliability.
The internal electric fields near the drain end of small geometry MOSFET""s are very high, resulting in carrier heating effects and hot electron degradation of devices. To reduce the electric fields, conventionally a lightly doped drain (LDD) is used in MOSFET""s where the doping level in the drain adjacent to the channel is reduced so that the electric field near the drain-channel junction can be lowered. However, the LDD approach has severe problems for deep submicron channel lengths since there is an unacceptable real estate penalty for the LDD regions. Further, the fields cannot be reduced sufficiently and the trapped hot electrons in the gate oxide can have serious depletion effects in the LDD region. Source/drain junction depths, especially the LDD junction depths, have to be made very shallow to avoid charge sharing effects such as threshold voltage, VT, lowering with reduction of the channel length, punch-through and drain induced barrier lowering. Additionally, there are source/drain series resistance problems associated with the shallow LDD region, and to a lesser degree with the shallow LDD regions. Also, there can be enhanced leakage in the LDD region due to band-to-band tunneling or gate induced drain leakage (GIDL). Further, there is a source/drain and gate overlap Miller capacitance and a large source/drain junction capacitance because of the high tank doping required for punch-through protection. All of these factors pose severe technological challenges in fabricating the devices, slow down circuit switching speeds, and increase active power dissipation.
In view of the drawbacks mentioned above, there is a continued need to develop new semiconductor device that overcome the disadvantages associated with prior art.
It is therefore an object of the invention to provide a semiconductor device with a trench isolation structure that can prevent drain induced barrier lowering (DIBL), punch-through leakage and spiking leakage without degrading the performance and the reliability of the semiconductor device.
It is another object of this invention to provide a semiconductor device with a trench isolation structure that can solve the poor electrical property of the conventional semiconductor device with a shallow junction depth and a short channel resulting from the shrink of design rules.
It is a further object of this invention to provide a new structure of semiconductor devices without the problems resulting from the shrink of design rules.
To achieve these objects, and in accordance with the purpose of the invention, the invention provides a semiconductor device with a trench isolation structure, said semiconductor device comprising: a substrate having a trench isolation, a source and a drain region therein, wherein said trench isolation isolates and is between said source and said drain region; a crystalline silicon layer over said substrate; a gate oxide layer on said crystalline silicon layer and above said trench isolation; and a gate electrode on said gate oxide layer.
The invention also provides a semiconductor device with a trench isolation structure, said semiconductor device comprising: a substrate having a trench isolation structure, a source region and a drain region therein, wherein said trench isolation structure isolates and is between said source and said drain region; a crystalline silicon layer over said substrate having a lightly doped drain region therein; a gate oxide layer on said crystalline silicon layer and directly above said trench isolation structure; and a gate electrode on said gate oxide layer, wherein said gate electrode has a spacer adjacent the sidewalls of said gate electrode.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.